Qwen3.8-Flash-Next / Qwen4-Exp kernel TDD ledger

This is the paired Iron ledger for branch codex/qwen38-flash-next-kernels-tdd. Butter owns model/loading/runtime policy; Iron owns backend-neutral kernel IR and CUDA/Metal lowering. No user working directory is used for this branch.

Canonical tracking issue: https://github.com/waffuruai/iron/issues/144.

Baseline I0 — 2026-08-26

• Iron base: de9c6e4525a868a1d540dcc4a64fa3aea88e5b79
• Isolated worktree: /Users/tom/dev/worktrees/iron-qwen38-flash-next-tdd
• Paired Butter branch: codex/qwen38-flash-next-tdd
• Butter currently pins older Iron SHA 4ed6461fdc6c61810d600f2828faf11e1ea79164. Baseline Butter tests stay on that lock until an Iron primitive requires a deliberate lockfile bump.
• CUDA is a first-class Iron target. CUDA-vs-Metal parity is required for backend-neutral primitives; GB10 CUDA is the initial hardware lane.

Method

Each primitive follows RED → scalar/reference oracle → shared Iron IR → CUDA and Metal lowering → differential/property tests → targeted benchmark. Temporary debug output must be gated by a Qwen-specific environment switch and removed or converted to structured tracing before merge.

Never optimize from a whole-model mismatch. Localize in this order:

1. FP8 PLE dequantization with scalar scale.
2. N-gram gather/split/reduce.
3. Gated residual merge.
4. GDN recurrent state update and chunk/decode equivalence.
5. QSA attention and cache semantics.
6. Sigmoid top-10 MoE routing.
7. NVFP4 W4A4 group-16 expert GEMM.

Next checkpoint

I1 RED begins after Butter T3 produces a header-validated tiny FP8 PLE fixture. Butter T2 confirmed the release has 128 F8_E4M3 [2500012,160] tables and one shared BF16 [1] weight_scale—not one scale per table. The first Iron test will compare FP8-E4M3 gather/decode times that scalar against an f32 oracle, including zero, extrema, NaN policy, tail lengths, and misdeclared scale shape. This prevents the known failure mode where a plain dtype upcast produces plausible but wrong PLE embeddings.