GLM-5.3-Flash kernel TDD ledger

Parent trackers: Butter #265, Iron #145.

Baseline: Iron de9c6e4525a868a1d540dcc4a64fa3aea88e5b79, branch codex/glm53-kernels-tdd. CUDA/GB10 is the real-model gate. Metal checkpoint execution is not required; backend-neutral tiny fixtures remain desirable.

Slice ledger

Slice	RED / mutation	GREEN requirement	Status
I0 final mHC head	Returning stream zero must differ from the four-stream mean	F32/F16/BF16, hidden 4096 decode plus multi-token fixture	Implemented; cargo check -p wh-iron-std --lib GREEN; filtered GPU run pending
I1 mHC split	Legacy row-final Sinkhorn differs from GLM’s column-final 20-step schedule	Exact pinned-reference fixture, CUDA ABI, row/column receipts	Explicit column_final schedule, 20-step test and zero-step underflow guard implemented; GPU run pending
I2 KDA decode	Wrong decay sign, missing beta/Q scale, low-precision state, or transposed state	Sequential independent F32 recurrence at 64×128	FP32 [value,key] state, clamp/exp and separate q_output_scale=1/sqrt(Dk) implemented; small and release geometry generated; GPU run pending
I2a KDA Q/K normalization	Reusing RMS norm, max(norm,eps), or one shared/bad binding	Independent F32 x/sqrt(sum(x²)+eps) oracle	Dedicated dual-buffer Q/K unit-L2 kernel plus F32/F16/BF16 generated fixtures and structural ABI test implemented; GPU run pending
I3 KDA convolution	One-position state shift	Step equals full width-4 causal convolution	Existing causal kernel qualified at concatenated 3×64×128 GLM geometry; GPU run pending
I4 KDA prefill	Token/chunk divergence at 63/64/65	Chunk path matches sequential state and output	FP32-register chunk kernel and all three boundary fixtures implemented; GPU run pending
I5 DSA pool/index	Mean pool, raw-slot alignment, omitted tail, unstable ties	Weighted k-pool and compact selected indices	Weighted pool now takes first_valid; seven-token tail and high-score left-padding fixtures implemented; host selector fixes stable ordering
I6 DSA/MLA	Dense mask accidentally used or NoPE layout transposed	Compact d256 sparse attention matches dense short-context oracle	Compact-index d256 decode kernel implemented with permuted-full-selection dense equivalence; GPU run pending
I7 MoE/FP8	BF16 router, wrong scale block, unstable top-8	288/top-8 F32 router plus 128×128 E4M3 grouped compute	Existing sigmoid + normalized selector qualified at 288/top-8; caller scale and quant compute remain artifact-dependent

Discovered contract boundary

iron_mhc_collapse and iron_mhc_expand match GLM’s state layout. The current iron_mhc_sinkhorn_split/Butter DSv4 helper performs column → row for every iteration. The pinned GLM reference performs initial column normalization and then row → column for the remaining 19 iterations, ending column-stochastic. iron_mhc_sinkhorn_split now has an explicit column_final constexpr. Legacy callers and benches use 0; GLM uses 1 with 20 steps. Both schedules remain visible in the ABI instead of being inferred from the model family.

Current compile receipt

CARGO_TARGET_DIR=/Users/tom/dev/build-cache/glm53-iron \
CARGO_INCREMENTAL=0 CARGO_PROFILE_DEV_DEBUG=0 RUSTFLAGS='-Cdebuginfo=0' \
cargo check -p wh-iron-std --tests

This compiles all declarative test definitions and kernel IR generation. It is not a GPU pass; this host has no CUDA device and the real generated runner is an explicit hardware gate.

The host-runnable glm5_abi_contract integration test additionally freezes Q/K buffer order, FP32 recurrence state, token_count, and the separate q_output_scale constexpr. This catches stale or reordered Butter bindings before a GPU launch.

Harness rule

Every kernel must be collected by Iron’s real generated GPU harness. An ordinary cargo test --lib that reports zero declarative GPU cases is not a GREEN result. On this machine broad runner builds are prohibited while disk headroom is below the documented safe threshold; use a private low-debug target and the narrow filtered runner when space is available.